32/64-bit Microprocessors Timeline

Motorola was late to the 16-bit microprocessor party, so it decided to arrive in style. The hybrid 16-bit/32-bit MC68000 packed in 68,000 transistors, more than double the number of Intel's 8086. Internally it was a 32-bit processor, but a 32-bit address and/or data bus would have made it prohibitively expensive, so the 68000 used 24-bit address and 16-bit data lines.

— Chip Hall of Fame: Motorola MC68000 Microprocessor (IEEE Spectrum, 30 June 2017)

Well the main thing that we did is we added complexity to the machine, especially in transitions. As we went up the chain a little bit to 68010, 68020, we created a monster in terms of all the addressing modes that we had. We thought that adding more addressing modes was the way you made a machine more powerful, totally contrary to the principle of RISC later.

This paper discusses the architecture from a number of points of view. It begins by making the distinction between architecture and implementation. The paper then states the overriding architectural goals and discusses a number of key architectural decisions that were derived directly from these goals. The key decisions distinguish the Alpha AXP architecture from other architectures. The remaining sections of the paper discuss the architecture in more detail, from data and instruction formats through the detailed instruction set. The paper concludes with a discussion of the designed-in future growth of the architecture. An Appendix explains some of the key technical terms used in this paper. These terms are highlighted with an asterisk in the text.

• Hewlett-Packard was realizing the future PA-RISC development would get more and more expensive, but the PA-RISC market was not growing. Eventually further development costs for a niche CPU would be economically non-viable.
• There was growing concern that further Out-of-Order performance scaling would be poor. A variation of VLIW was seen as a way to get around this. HP was exploring VLIW architectures.
• Intel was unhappy about the existence of x86 clone vendors, especially AMD.
• The x86 architecture was limited to 32-bit addresses and this was expected to be a problem in the near future. A 64-bit machine would address this problem.

• For Intel and HP to jointly develop a new CPU architecture. Intel would be responsible for manufacturing the chips.
• The architecture would be VLIW instead of Out-of-Order Superscalar.
• The architecture would be 64-bit rather than 32-bit.
• The instruction set could be protected by patents that would prevent clones.

Silicon Graphics Inc., the leading maker of the computer work stations that engineers, architects and movie artists use to fashion three-dimensional images, said today that it was buying MIPS Computer Systems Inc. in a stock swap valued at about $406.1 million.

The merger will unite two of Silicon Valley's leading electronics companies to create an enterprise with revenues approaching $1 billion.

MIPS designs the microprocessors that serve as the brains for many of the most powerful desktop computers, including the work stations made by Silicon Graphics. Once hailed as the next Intel Corporation for its advanced designs, MIPS has suffered from inconsistent profits and employee defections, including the departure last month of the company's president, Charles M. Boesenberg.

Customers have been departing as well. Prime Computer and Groupe Bull of France recently stopped making computers based on MIPS chips. And Digital Equipment, MIPS's largest customer, has said it will begin producing a competing microprocessor of its own.

Silicon Graphics is so dependent on the MIPS microprocessor that it has already gone so far as to develop its own version of the chip, and was reported to be in talks with Toshiba of Japan about manufacturing it.

...

The close relationship between Silicon Graphics and MIPS dates to the early 1980's, when the founders of both companies were all professors at Stanford University. Silicon Graphics was the first customer for MIPS's chip designs.

Motorola Inc. stepped up its increasingly heated race with the Intel Corporation yesterday, introducing a new generation of microprocessors that it said could put the power of a mainframe computer on a single chip. The new chip, called the Motorola 68030, comes only two and a half years after the introduction of the company's current top-of-the-line microprocessor, the 68020. Motorola said the new chip would offer nearly twice the performance of its predecessor but would not be delivered until March 1987. Motorola's new entry comes just a week after Intel's top-of-the line microprocessor was incorporated for the first time in an I.B.M.-compatible personal computer, made by the Compaq Computer Corporation. "Our effort is to maintain a performance advantage of 300 to 400 percent over the competition," said Murry Goldman, a Motorola senior vice president.

The WE 32100 Microprocessor (CPU) is a high- performance, single-chip, 32-bit central processing unit designed for efficient operation in a high-level language environment. It performs all the system address generation, control, memory access, and processing functions required in a 32-bit microcomputer system. It has separate 32-bit address and data buses. System memory is addressed over the 32-bit address bus by using either physical or virtual addresses. Data is read or written over the 32-bit bidirectional data bus in word (32-bit), halfword (16-bit), or byte (8-bit) widths. Extensive addressing modes result in a symmetric, versatile, and powerful instruction set. The WE 32100 Microprocessor is available in 10-, 14-, and 18-MHz versions...

Features:

• Powerful and versatile instruction set
• On-chip instruction cache
• 4 Gbytes (2³²) of direct memory addressing
• Physical and virtual addressing
• Coprocessor interface
• DMA and multiprocessor environment support
• 15 levels of interrupts
• Autovector and nonmaskable interrupt facilities
• Four levels of execution privilege: kernel, executive, supervisor, and user
• Synchronous or asynchronous interfacing to external devices
• Nine 32-bit general-purpose registers
• Seven 32-bit special-purpose registers
• Memory-mapped I/O
• Complete floating-point support via the WE 32106 Math Acceleration Unit

SAN FRANCISCO — AT&T's Bell Laboratories recently announced a second-generation, 32-bit microprocessor said to take advantage of the Unix operating system and planned to be used in a series of AT&T 3B computers.

The chip, called the WE 32100, is the successor to the WE 32000, which was formerly known as the Bellmac-32A. It reportedly contains 180,000 transistors, about 30,000 more than the earlier chip, and uses Cmos technology.

"We have integrated many support functions onto the chip," said Hing C. So, head of the Very Large Scale Integration Department at Bell Labs. "We have also added features such as an internal cache memory and have increased the speed of the chip."

The cache memory reportedly can hold 64 32-bit words, and repeatedly used program instructions can be stored there so there is no waiting time, a spokesman said.

The WE 32100 reportedly operates at speeds up to 14 MHz, is packaged in a 132-pin package and dissipates approximately 1.9W in worst-case conditions.

— Computerworld, March 19, 1984, p104

The WE 32200 Microprocessor (CPU) is a high-performance, single-chip, 32-bit central processing unit designed for efficient operation in a high-level language environment. It is protocol and upward object code compatible with the WE 32100 Microprocessor. The WE 32100 CPU runs object code without modification on the WE 32200 CPU. The WE 32200 CPU performs all the system address generation, control, memory access, and processing functions required in a 32-bit microcomputer system. It has separate 32-bit address and data buses. System memory is addressed over the 32-bit address bus by using either physical or virtual addresses. Data is read or written over the 32-bit bidirectional data bus in word (32-bit), halfword (16-bit), or byte (8-bit) widths, using arbitrary byte alignment for data and instructions. Dynamic bus sizing allows the WE 32200 CPU to communicate with both 16-bit and 32-bit memories in the same system. Extensive addressing modes result in a symmetric, versatile, and powerful instruction set. The WE 32200 Microprocessor is available in 24-MHz and higher frequency ...

Features:

• 32-bit virtual memory microprocessor with 4 Gbytes (2³²) virtual memory space and up to 4 Gbytes physical addressing space
• Efficient execution of high-level language programs
• Extensive and orthogonal instruction set with 25 addressing modes
• Arbitrary byte alignment for data and instructions
• Direct support for process-oriented operating systems, such as UNIX System V
• WE 32100 Microprocessor object code and protocol compatible
• Four levels of execution privilege: kernel, executive, supervisor, and user
• Fifteen levels of interrupt
• High-performance, on-chip, 64 x 32 bit instruction cache
• Byte replication on writes
• Dynamic bus sizing for 16-bit and 32-bit data and instructions
• Seventeen 32-bit general-purpose registers
• Eight 32-bit general-purpose privileged registers
• Seven 32-bit special-purpose registers
• Memory-mapped I/O
• Complete ANSI/IEEE Standard 754 floating-point support via the WE 32206 MAU Coprocessor
• Development system support signals
• General-purpose coprocessor interface
• Synchronous or asynchronous interfacing to external devices
• High priority two-wire bus arbitration through relinquish and retry

The American Telephone and Telegraph Company introduced a family of computer chips yesterday that includes a faster microprocessor than any yet brought to market.

Industry analysts said that, despite the chip's speed, its prospects were somewhat limited because A.T.&T. lacked relationships with computer makers that would be likely to incorporate the chip into their computer designs.

The WE 32200 microprocessor and related chips would be used to make top-of-the-line microcomputer systems that could handle several users doing several jobs at once, A.T.&T. said. A microprocessor is the brain inside personal computers and engineering work stations. The chips are taking work away from minicomputers and mainframes because they do some of the same jobs far more cheaply.

The WE 32200 will cost $500 each in quantities of 100 and is scheduled to be available in production quantities in the second half of 1987, A.T.&T. said. The chip will run at speeds starting at 24 million cycles a second and will be available at 30 million cycles a second by the end of 1987, the company said.

NS32532-20/NS32532-25/NS32532-30
High-Performance 32-Bit Microprocessor

General Description
The NS32532 is a high-performance 32-bit microprocessor in the Series 32000 family. It is software compatible with the previous microprocessors in the family but with a greatly enhanced internal implementation.

The high-performance specifications are the result of a four-stage instruction pipeline, on-chip instruction and data caches, on-chip memory management unit and a significantly increased clock frequency. In addition, the system interface provides optimal support for applications spanning a wide range, from low-cost, real-time controllers to highly sophisticated, general purpose multiprocessor systems.

The NS32532 integrates more than 370,000 transistors fabricated in a 1.25 mm double-metal CMOS technology. The advanced technology and mainframe-like design of the device enable it to achieve more than 10 times the throughput of the NS32032 in typical applications.

In addition to generally improved performance, the NS32532 offers much faster interrupt service and task switching for real-time applications.

Features

• Software compatible with the Series 32000 family
• 32-bit architecture and implementation
• 4-GByte uniform addressing space
• On-chip memory management unit with 64-entry translation look-aside buffer
• 4-Stage instruction pipeline
• 512-Byte on-chip instruction cache
• 1024-Byte on-chip data cache
• High-performance bus
  • Separate 32-bit address and data lines
  • Burst mode memory accessing
  • Dynamic bus sizing
• Extensive multiprocessing support
• Floating-point support via the NS32381 or NS32580
• 1.25 mm double-metal CMOS technology
• 175-pin PGA package

• Slower but less expensive off-chip L2 caches
• A larger L1 cache (16+16 KB vs 8+8 KB for Pentium Pro)
• Better 16-bit performance (important for lots of existing code)

An out-of-order, three-way superscalar x86 microprocessor with a 15-stage pipeline, organized to allow 600-MHz operation, can fetch, decode, and retire up to three x86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously dispatch up to nine operations to seven integer and three floating-point execution resources. The cache subsystem and memory interface minimize effective memory latency and provide high bandwidth data transfers to and from these execution resources. The processor contains separate instruction and data caches, each 64 KB and two-way set associative. The data cache is banked and supports concurrent access by two loads or stores, each up to 64-b in length. The processor contains logic to directly control an external L2 cache. The L2 data interface is 64-b wide and supports bit rates up to 2/3 the processor clock rate. The system interface consists of a separate 64-b data bus. The die, shown in Fig. 1, is 1.84 cm and contains 22 million transistors. Table I shows the technology features. C4 solder-bump flip-chip technology is used to assemble the die into a ceramic 575-pin ball grid array (BGA). Measurements are from initial silicon evaluation unless otherwise stated.

Silicon Graphics scraps MIPS plans
Silicon Graphics (SGI) has quietly scrapped ambitious plans for its MIPS processors and is now following a much more limited road map calling for fewer design improvements, according to sources close to SGI.

The last major MIPS release for servers and workstations is scheduled for 1999, sources said.

MIPS roadmap

Model	Speed	Status
R10000	250 MHz	available now
R12000	300 MHz	due mid 1998
R14000	400 MHz	due 2H 1999
"Beast"	N/A	canceled
"Capitan"	N/A	canceled

SGI will continue to boost processor speeds and incorporate the chip in its high-end computers, but will likely start the phasing out the processor in 2001 as 64-bit chips from Intel become more pervasive and powerful.

The TS-1 was the first PA-RISC production processor, introduced in 1986. It integrated version 1.0 of PA-RISC on six 8.4×11.3" boards of TTL and was used in HP 9000 840 servers, the first PA-RISC computers.

The basic types of operations in most instruction sets fall into three categories: data transformation operations, data movement operations, and control operations. In general, one instruction performs one of these operations. A combined instruction performs more than one of these operations in one instruction. In HP Precision Architecture, almost every instruction performs a combination of two of these operations in a single cycle, with relatively simple hardware.

(emphasis added)

HP Precision Architecture is frequently referred to as a reduced instruction set computer (RISC) architecture. Indeed, the execution model of the architecture is RISC-based, since it exhibits the features of single-cycle execution and register-based execution, where load and store instructions are the only instructions for accessing the memory system. The architecture also uses the RISC concept of cooperation between software and hardware to achieve simpler implementations with better overall per formance.

HP Precision Architecture, however, goes beyond RISC in many ways, even in its execution model. For example, RISC machines emphasize reducing the number of instructions in the instruction set to simplify the implementation and improve execution time. Only the most frequently used, basic operations are encoded into instructions. How ever, frequency alone is not sufficient, since some instructions may occur frequently because of inefficient code generation, arbitrary software conventions, or an inefficient architecture.

In designing the next-generation architecture for Hewlett-Packard computers, the intrinsic functions needed in different computing environments like data base, computation intensive, real-time, network, program development, and artificial intelligence environments were determined. These intrinsic functions are supported efficiently in the architecture. Minimizing the actual number of instructions is not as important as choosing instructions that can be executed in a single cycle with relatively simple hardware. Complex, but necessary, operations that take more than one cycle to execute are broken down into more primitive operations, each operation to be executed in one instruction. If it is not practical to break these complex operations into more primitive operations, they are defined as assist instructions, by means of the architecture's instruction extension capabilities. If more than one useful operation can be executed in one cycle, HP Precision Architecture defines combined operations in a single instruction, resulting in a more efficient use of the execution resources and in im proved code compaction.

HP Precision Architecture's execution model has other noteworthy features like its heavy use of maximal-length immediates as operands for the execution engine, and its efficient address modification mechanisms for the rapid access of data structures. The architecture also includes some uncommon functions for efficiently supporting the movement and manipulation of unaligned strings of bytes or bits, and primitives for the optimization of high-level language programs.

• Both are out-of-order (and the 1st out-of-order CPUs in their families)
• Three instructions/clock max for the Pentium Pro and four for the PA-8000
• 180 - 200 MHz
• Large off-chip caches

Why did we design the processor without on-chip caches? The main reason is performance. Competing designs incorporate small on-chip caches to enable higher clock frequencies. Small on-chip caches support benchmark performance but fade in large applications, so we decided to make better use of the die area. The sophisticated instruction reorder buffer allowed us to hide the effects of a pipelined two-state cache latency. In fact, our simulations demonstrated only a 5% performance improvement if the cache was on chip and had a single-cycle latency. A flat cache hierarchy also eliminates the design complexity associated with a two-level cache.

• Introduced: 1996
• Super-scalar (4-issue), Pipelined, Out-of-order
• On-chip caches: None
  Off-chip cache: Up to 4 MB L1 (separate die)
• FPU: On-chip
• Up to 180 MHz
• 3.8M transistors
• Die Size: 338 mm² (not counting separate cache die)

• THE HP PA-8000 RISC CPU
• PA-8000 Combines Complexity and Speed
• Hot Chips VIII Presentation: The HP PA-8000 RISC CPU

The bottom performance line as measured by these four small programs is that the newest version of the 432 (8 MHz with 4 wait states) is almost as fast as a 5 MHz 8086, while the 80286 leads the 432 by almost an order of magnitude.

Update On 32-Blt Microprocessors: The International Solid-State Circuits Conference (ISSCC) met in New York last February and heard presentations on two 32-bit microprocessors and some disclosures on a third.

Intel released further details on its 32-bit iAPX432 processor. It is Intel's first departure from previous architecture and instruction sets, so there is no software compatibility with its 8086 (16-bit) and 8085 (8-bit) microprocessors. Each of the iAPX432's three integrated circuits has four lines of sixteen pins. There are two general processors and an I/O (input/output) processor. The iAPX432 can link to 8086s and existing peripheral and memory integrated circuits. Intel is boasting performance of up to 2 MIPS (million instructions persecond).

It took five years to engineer the iAPX432, and the company estimates that $25 million was spent on the project. Intel expects to sell at least 10,000 sets in the first year of production, which is projected for 1982. The initial price for the set will be $1500. Intel started shipping evaluation sets in February and is offering a board-level evaluation kit for $4250.

Intel claims that each of the three integrated circuits contains about 200,000 transistors. Two chips operate as a pipeline pair: the 43201 processor, which contains the instruction decoder, and the 43202, which is the microexecution unit. The 43203 is the I/O processor. It provides an interface from the I/O subsystem to the protected-access environment of the central system. Each I/O subsystem uses an 8- or 16-bit microprocessor to control I/O, independent of the central system. An address space of more than 4 gigabytes (4×10⁹ bytes) and a virtual memory-address space of a terabyte (10¹² bytes) is supported.

A protection scheme is provided to limit access to programs. The iAPX432 can perform floating-point operations on 32-, 64-, and 80-bit numbers. Hardware failures can be detected by interconnecting identical iAPX432 processors in a self-checking arrangement.

The system uses compiled Ada code as its machine language. The language interpreter is contained in a 64 K-byte microcode ROM (read-only memory).

Intel has also released an Ada cross-compiler for the iAPX432. The compiler runs on a DEC (Digital Equipment Corporation) VAX-11/780 or an IBM 370. It costs $30,000. A $50,000 hardware link is needed to download the compiled code to Intel's $4250 development board.

With the iAPX432, Intel appears to have a two-year jump on its competition. At the conference, Hewlett-Packard (HP) disclosed that it is in the early stages of development on a 32-bit microprocessor. HP claims to have built and tested a single chip with 450,000 transistors (which is about what Intel has in its set of three integrated circuits).

Intel has also stopped all manufacturing, marketing, and support activities for its 432 microprocessor. The 432 was Intel's first 32-bit chip set. but it was never used in any large volume computers. Intel is reportedly working on two other 32-bit chip designs, including the Intel 80386, which will be compatible with its 80286 and earlier designs. Intel will begin shipping samples of the 80386 late this year.

NCR/32 Processor Family Features

• 32-bit system architecture
• 13.3 Megahertz frequency
• Effective emulation of mid-range mainframes
• Externally microprogrammable
• Real and virtual memory operation
• Large direct memory addressing
• Interface provided to slower peripherals
• On-chip error check and correction

Functional Description
The NCR/32 VLSI Processor family combines the latest advances in semi-conductor technology with experience gained in three generations of computer mainframe design to provide a comprehensive microprogrammabie 32-bit system architecture. With external microprogram capability, an extremely flexible microinstruction set, and a powerful set of internal registers, the NCR/32 offers flexibility and high performance advantages not available with other microprocessors.
Along with an existing set of VLSI family support devices, the NCR/32 offers effective emulation of register, stack and descriptor-based system architectures, as well as execution of high-level languages directly from microcode. The NCR/32 is well suited for applications requiring direct addressing of a large memory space, high numeric precision, and very-high-speed execution such as bit-mapped graphics, robotics, artificial intelligence, and relational databases.

The NCR NCR/32. This microprocessor chip set is quite different from all of the other microprocessors discussed in this article. It is designed to be externally microprogrammed to emulate other computers, principally medium-sized IBM mainframes like the System 370. The chip set consists of:
*) the NCR 32-000 CPC, the central processing unit. It contains 40,000 transistors and is fabricated in a 3-micron silicide NMOS process. It runs with a 13.3-MHz clock, with internal machine cycles occupying two clock cycles (150 nanoseconds). The 16-bit microinstructions, read from a 128K-byte external storage unit, select 95-bit words from an internal ROM to control 179 operations, mostly register-to-register arithmetic and logical operations on 4-bit, 8-bit, 16-bit, 32-bit, and field data types. Microinstructions are executed in a three-stage pipeline (fetch, interpret, execute). Eight 16-bit jump registers support a rich set of conditional operations at the microcode level, and special set-up microinstructions facilitate IBM System 370 emulation
*) the NCR 32-010 ATC, the memory management unit. In addition to address translation and access protection, this chip provides memory-refresh control, error-checking and correction (ECC) logic, a time-of-day register, an interval timeout interrupt, and an interrupt on writes to one specified virtual address. Sixteen translation registers support mapping of 32-bit or 24-bit virtual addresses into 24-bit physical addresses, using page sizes of 1K, 2K, or 4K bytes.
*) the NCR 32-020 EAC, the "booster" chip for arithmetic operations. It supports IBM-compatible single- and double-precision binary and floating point arithmetic, packed and unpacked decimal storage, and format conversions. A single-precision floating-point addition takes approximately 1.6 microseconds.
*) the NCR 32-500 SIC, which interfaces the 24-megabyte/second prcessor memory bus to slower peripherals and to other systems. The configuration of an NCR/32 system is shown in figure 3. No benchmark data has been published, but NCR estimates performance of the NCR/32 at approximately four times that of a 10-MHz 68000.

1.1 INTRODUCTION

The Z80,000 CPU is an advanced 32-bit microprocessor that integratea the architecture of a mainframe computer into a single chip. A subset of the Z80,000 architecture was originally implemented in a 16-bit version, the Z8000 microprocessor. The Z80,000 bus structure permits the use of Z8000 family peripherals, such as the Z8030 SCC and Z8036 CIO. While maintaining compatibility with Z8000 family software and hardware, the Z80,000 CPU offers greater power and flexibility in both its architecture and interface capability. Operating systems and compilers are easily developed in the Z80,000 CPU's sophisticated environment, and the hardware interface provides for connection in a wide variety of system configurations.

Memory management is integrated in the CPU, providing access to more than 4 billion bytes of logical address space without external support components. The Z80,000 CPU also includes a cache memory, which complements the pipelined design to achieve high performance with moderate memory speeds.

This chapter presents an overview of the features of the Z80,000 CPU that offer extraordinary flexibility to microprocessor system designers in tailoring the power of the CPU to their specialized applications. The chapters that follow describe these features in detail.

1.2 ARCHITECTURE

The CPU features a general-purpose register file with sixteen 32-bit registers. The instruction set offers a regular combination of nine general addressing modes with operations on numerous data types, including bits, bit fields, bytes (8 bits), words (16 bits) , long words (32 bits) , and variable-length strings. The memory management, exception handling, and system and normal mode features support the development of reliable software systems.

1 .2.1 Registers The Z80,000 CPU includes sixteen 32-bit general-purpose registers. The registers can be used as data accumulators, index values, or memory pointers. Two of the registers, the Frame Pointer and Stack Pointer, are used for procedure linkage with the Call, Enter, Exit, and Return instructions.

The Z80,000 registers also include the 32-bit Program Counter and 16-bit Flag and Control Word. These two registers, together called the Program Status, are automatically saved during trap and interrupt processing. Nine other special-purpose registers are used for memory management, system configuration, and other CPU control.

1.2.2 Address Spaces

The CPU uses 32-bit logical addresses, permitting direct access to 4G bytes of memory. The logical addresses are translated by the memory management mechanism to the physical addresses used to access memory and peripherals.

The CPU supports three modes of address representation — compact, segmented, and linear — selected by two control bits in the Flag and Control Word register. Applications with an address space smaller than 64K bytes can take advantage of the dense code and efficient use of base registers with the 16-bit compact addresses. Although programs executing in compact mode can only manipulate 16-bit addresses, the logical address is extended to 32 bits by concatenating the 16 most-significant bits of the Program Counter register. Compact mode is equivalent to the Z8000 non-segmented mode.

Segmented mode supports two segment sizes — 64K bytes and 16M bytes. Up to 32,768 of the small segments and 128 of the large segments are available. In segmented mode, address calculations do not affect the segment number, only the offset within the segment. Allocating individual objects such as program modules, stacks, or large data structures to separate segments allows applications to benefit from the logical structure of a segmented memory space.

The 32-bit addresses in linear mode provide uniform and unstructured access to 4G bytes of memory. Some applications benefit from the flexibility of linear addressing by allocating objects to arbitrary positions in the address space.

Problems in debugging complex microprocessor chips have caused new problems at Zilog and Intel. Zilog admitted that sampling of its Z80000 32-bit processor. announced in the summer of 1983. has been delayed until early 1986. Zilog had originally planned to start shipping the Z80000 in late 1984

The instruction encoding is designed with two primary considerations. First, the instruction length must be easily determined. Therefore, the length is encoded in the first two bits of each instruction. Since all instructions are multiples of two bytes, this unit is referred to as an instruction parcel. Second, static and dynamic code size should be made as small as possible without interfering with performance issues. Instructions that require two 32-bit addresses or operands, can use the five parcel form shown in Figure 1. The three parcel form can be used to provide a single 32-bit operand or two 16-bit operands. The single parcel format has a 5-bit opcode field which defines the most frequent combinations of operations and addressing modes occurring in the three and five parcel forms. This highly encoded single parcel form typically accounts for 80 percent of all instructions.

The AT&T Hobbit Enters Its Second Generation

The AT&T Hobbit chip sets betray their corporate heritage. These are chips designed first and foremost for telecommunications applications. AT&T Microelectronics first offered a set of chips for PDAs (personal digital assistants) in 1992. The 92K Hobbit family, the chips that are used in the Eo Personal Communicator, has five parts: a CPU, a system controller, a bus controller, a video-display controller, and a peripheral-bus controller.

The price seemed high at $99 for the chip set, but it was complete. Late last year, AT&T introduced two new chip sets designed to broaden the line, with trade-offs in performance, system size, cost, battery life, and feature sets.

The ATT92020S processor provides higher performance — it uses a 6-KB prefetch buffer as opposed to the 3-KB buffer on the 92010 — and requires less power than the original 92010 CPU, It also works with all the existing 92010 support chips except for the ISA controller. ISA support doesn’t figure very highly in the new Hobbit offerings.

TRON microprocessors will also be in competition with new RISC chips, for unlike RISC architectures the TRON CPU has a compiler-oriented CISC structure that allows it to compile high-level program code efficiently.

TRON microprocessor manufacturers include Toshiba, developing its TX series, and the GMICRO group of Hitachi, Fujitsu and Mitsubishi. Oki Electric, which is now participating in development of the GMICRO series, is also working on its own TRON CPU. Matsushita similarly is producing its own TRON chip (see Table 1 over).

The most ambitious design is Toshiba's TX3, a 1.2M transistor, 33 MIPS (peak) microprocessor due late in 1990, intended for high-end workstations. Already available is the TX1 embedded controller, which is pin compatible with the TX3. The TXl can also be used as an ASIC macro cell.

Toshiba is also developing three peripheral chips for the TX series: a 50 MHz clock generator, an interrupt controller/timer that can handle up to eight interrupts, and a four channel direct memory access controller (DMAC) with 50 and 25 Mbyte s^-1 block and single transfer modes.

The GMICROgroup plans to unveil a 900k transistor, 20 MIPS TRON CPU, the GMICRO/300, in the current quarter. Unlike the TX3, which will basically have a floating-point unit (FPU) built into it, the GMICRO/300 will use an external FPU. To allow for efficient interaction with the FPU, and easy development of software, the GMICRO/300 will have 22 coprocessor instructions, in addition to 11 decimal instructions. The other peripheral chips in the GMICROseries are a cache controller/memory, a four channel DMAC, an interrupt request controller that can handle up to seven interrupts, a tag memory with a 27 µs access time, and a 40-48 MHz clock pulse generator.

The GMICRO series began in 1987 with the appearance of the 730k transistor, 10 MIPS GMICRO/200, followed recently by the GMICRO/100 embedded controller with 330k transistors (operating speed 10 MIPS (max.)). High-speed versions of all three GMICRO microprocessors are planned by equipping them with 33 MHz clocks.

Oki Electric has joined the GMICRO group to market the series products and to undertake the development of GMICROevaluation tools that operate in the BTRON environment.

Prior to joining GMICRO, Oki was reported to be developing the 032 chip, but no launch date has been announced. Unlike the other developers who are planning different chips for different applications, Oki intends to use its CPU across a variety of applications from embedded controllers to communications terminals and lower-performance PC devices. Similarly, Matsushita anticipates wide application of its MN10400, a 400 k transistor, 20 MIPS chip due this quarter.

• Was constrained to a 40-pin package (for cost reasons) rather than an 82-pin package.
• Was assembly source compatible with the 8080
• Had hardware integer multiply

Exponential Unveils Fast Chip: A San Jose start-up company announced the speediest microprocessor yet, a chip able to run Macintosh software at up to 533 megahertz, more than twice as fast as current chips. Exponential Technology Inc. said its X-704 chip should be available in volume next spring. The company is one of several chip makers to unveil new products at the Microprocessor Forum this week in San Jose. The four-day conference marks the 25th anniversary of the microprocessor. Exponential started in 1993, with financial help from Apple Computer Inc. George Taylor, Exponential's founder and chief technology officer, says the new chips will cost about $1,000 each, which would put them into high-end computers used mostly by graphic designers and creators of multimedia. Industry analysts said Exponential's chip could give Apple's Macintosh computers a boost.

The National Semiconductor Corporation has agreed to sell the rights to the Clipper microprocessor product line to the Intergraph Corporation. The sale, for what industry officials said was about $10 million, indicates that National is quickly moving to sell parts of the Fairchild Semiconductor Corporation, which it agreed to acquire from Schlumberger Ltd. last month for $122 million in stock.

National was expected to divest itself of Fairchild's microprocessor business because it already had its own. Intergraph, a Huntsville, Ala., company that makes systems for computer-aided design, uses the high-speed Clipper chip in a work station. The company is so dependent on the chip that it had considered buying a stake in Fairchild as part of a management buyout effort. Intergraph is expected to offer jobs to about 100 Fairchild employees.

— New York Times, Sept. 18, 1987

The effective demise of the Intergraph Corp Clipper RISC chip is reported by our sister publication ClieNT Server News. Intergraph turned its California-based Advanced Processor Division over to Sun Microsystems Inc on January 1 and the 70-employee unit along with general manager Howard Sachs has become part of Sparc Technology Business unit which is working on marrying the Windows NT operating system to the Sparc chip. No further Clipper development is planned.